The present invention relates to semiconductor memory devices, and more particularly to circuits useful for transferring data into and out from these devices.
Memory devices are so large and complex that manufacturing defects are likely to exist in any given device. Any defects normally require repair after manufacture, by identifying defective portions of a device, and replacing the function of all defective portions with spare circuits built into the device for this purpose. The cost of test and repair is a significant portion of the total cost of a memory device. Data compression methods can minimize time required for test and repair, thus minimizing this cost component.
Data compression is a technique to speed memory testing by writing and/or reading more memory cells than normal during each memory access. Data compression utilizes simplified test patterns, with many bits written to the same state, such as all ones, all zeroes, bars, or checkerboard, enabling the testing of many cells per access by logical comparison. For example, if all zeroes have been written to a memory, and then the cells are read a dozen at a time, one can detect whether or not the data as read correctly contains all zeroes by gating a logical OR of the data from the dozen cells onto a data line, whereupon the data line signal is zero for test-pass, and one for test-fail. When used this way, the signal on the data line becomes a compressed representation of the data stored in the dozen cells being read.
U.S. Pat. No. 6,163,863, issued Dec. 19, 2000 to Schicht, describes prior art in data compression. This patent implements a compression test mode data path requiring complex first and second stage data compression circuits, as shown in FIG. 5 of the Schicht patent by reference numerals 502, 504, 506, 508, 514 and 516. Using more circuits than necessary has the disadvantages of increasing die size and power consumption, adding wires for interconnect, and causing undesirable differences in electrical parameters, such as additional gate delays, between the circuitry used for testing and that used for normal operation. The Schicht patent has the further disadvantage of using separate wires to feed out compressed test data and normal mode data, making this design difficult to scale up when adding more memory sections to the compression test scheme.
U.S. Pat. No. 6,556,487, issued Mar. 12, 2002 to Merritt, discloses further prior art relevant to the current invention. FIG. 1 illustrates an aspect of compression as disclosed by this patent. FIG. 1 shows four flip-flops 122. In normal mode, each flip-flop drives one of the data bus lines D0–D3. In compression test mode, each flip-flop conveys complementary data to a first-level compression circuit 110. Each first-level compression circuit then feeds a second-level compression circuit 120. The second-level compression circuit then conveys compressed data from the four flip-flops onto data bus lines D2, D3.
The Merritt patent requires the following non-essential elements: separate data bus wires for writing and for reading, more than one level of compression circuits, wiring for interconnecting compression circuits, dummy devices to balance loads on both sides of the flip-flop, and an output circuit for separating the signals from the flip-flop. These non-essential elements have the disadvantages of increasing die size and power consumption without improving performance. The design disclosed by the Merritt patent has the further disadvantage of requiring added device loading on the data bus lines to support compression. As shown in FIG. 1, compression circuit 120 adds both p-type device and n-type device loading on data bus lines D2 and D3. This added loading inevitably slows down the read cycle. The Merritt design has the further disadvantage that it is not easily scalable by adding more memory sections to the compression scheme, since it requires more wires when adding more compression circuit blocks.